1. Field of the Invention
The present code tracking system relates to digital code tracking systems of the type employed in data link receivers. More particularly, the present invention relates to a novel PN code recovery and tracking system speed having a high speed code recovery and tracking portion superimposed on a low speed code recovery and tracking portion which results in higher PN code rates than was heretofore obtainable.
2. Description of the Prior Art
Heretofore it was known that two or more PN component codes could be combined to create a longer and more complex composite code. Our U.S. Pat. No. 4,809,295 describes a method and apparatus for generating a composite code having correlation properties between the component codes. However, the patent relates to component codes being run on the same clock, thus, are employing the same composite code rate as the component code rate.
In our U.S. Pat. No. 5,099,494, we described a digital demodulator for a PN code receiver. The front end of this receiver was described as being analog for processing real and imaginary signals which were converted to digital signals before being applied to the digital demodulator and digital acquisition and tracking loop. The system described in this patent was implemented in state-of-the-art CMOS technology chips whose PN chip rate is limited to a range of approximately 30 to 70 Mega chips per second.
It is well known that Gallium Arsenide (GaAs) technology chips are now capable of switching at rates of 500 to 1,000 megahertz. Even though GaAs chip technology permits faster switching rates, it is presently impossible to produce GaAs integrated circuit chips having the same density as CMOS chips and it would not be possible to make the digital circuits shown in our aforementioned U.S. Pat. Nos. 5,099,494 using GaAs technology. It would be highly desirable to produce an analog and/or a digital PN code receiver capable of producing PN code rates greatly in excess of the present CMOS limitation rate of 30 to 70 Mega chips per second using present state-of-the-art VLSI CMOS chip technology.